1. Field of the Invention
This invention relates to input/output (I/O) buffers for use in integrated circuits (IC), and more particularly, to an I/O buffer for use in an IC device, which is capable of accepting an input logic signal higher in voltage level than the system voltage.
2. Description of Related Art
Conventionally, most IC devices are driven by a system voltage in the range of 0-5 V (volt). In these IC devices, the high-voltage logic signal is therefore set at the system voltage and the low-voltage logic signal is set at the ground voltage. With advances in semiconductor technology, however, the system voltage can be now reduced to 3.3 V because the gate oxide layers in the IC device can be made thinner. Still lower system voltage may be possible in the future. In practice, however, a new 3.3 V IC device is usually used in conjunction with some old 5 V peripheral devices. For instance, a new 3.3 V VGA (video graphic adapter) IC may be used in conjunction with other old 5 V peripheral devices in a personal computer. Therefore, the compatibility between the new 3.3 V devices and the old 5 V devices is a problem in the use of the new 3.3 V devices.
FIG. 1 is a schematic circuit diagram showing the circuit structure of a conventional I/O buffer used in a 3.3 V IC device, which is the part that is enclosed in the dashed box indicated by the reference numeral 14. As shown, the I/O buffer 14 is coupled to an input buffer 16 and an I/O pad 20 of the IC device. The I/O buffer 14 is composed of a first circuit 10, a second circuit 12, a PMOS transistor P1, and an NMOS transistor N1. When the I/O buffer operates in input mode, both the PMOS transistor P1 and the NMOS transistor N1 must be switched to a non-conducting state. To do this, the first circuit 10 outputs a high-voltage signal, for example 3.3 V, to the gate of the PMOS transistor P1, thereby switching the PMOS transistor P1 into a non-conducting state.
Meanwhile, the second circuit 12 outputs a low-voltage signal, for example 0 V, to the gate of the NMOS transistor N1, thereby switching the NMOS transistor N1 into a non-conducting state.
If the I/O pad 20 receives a 5 V input logic signal, it causes the PMOS transistor P1 to be subjected to a gate voltage of 3.3 V, a drain voltage of 5 V, and a source voltage of 3.3 V. Since the gate voltage (3.3 V) is lower than the drain voltage (5 V) at the PMOS transistor P1, the gate voltage causes the PMOS transistor P1 to be switched into a reverse conducting state. Moreover, since the PMOS transistor P1 is formed on an N-type substrate (or an N-well, which is typically equipotential with the source) and its source and drain are both P-type, a PN junction diode as indicated by the reference numeral 18 is formed between its drain and the N-well. Furthermore, since the drain of the PMOS transistor P1 is connected to the I/O pad 20, which is now receiving the 5 V input logic signal which is higher than the 3.3 V system voltage, and the substrate thereof is connected to the 3.3 V system voltage, the PN junction diode 18 will be subjected to a forward bias, thus causing an undesired large current to flow between the external 5 V source and the internal 3.3 V source.
As a solution to the foregoing problem, an improved I/O buffer for the 3.3 V IC devices has been proposed, which is published in the IEEE JSSC, July, 1995. FIG. 2 is a schematic diagram showing the circuit structure of this improved I/O buffer. In this diagram, the symbol "+" represents the application of a 3.3 V system voltage.
When this I/O buffer operates in output mode, the signal OEN=0 is issued to the I/O buffer, which then causes the gate voltage at the PMOS transistor P4 to be 0. As a result, the PMOS transistor P4 is switched into a conducting state, thereby causing the 3.3 V system voltage to be applied to the floating N-well 22.
On the other hand, when this I/O buffer operates in input mode, the PMOS transistor P1 and the NMOS transistor N1 are both switched into a non-conducting state, causing a 3.3 V high-voltage signal to be applied to the gate of the PMOS transistor P1 and a 0 V low-voltage signal to be applied to the gate of the NMOS transistor N1. As a result of this, if a 5 V input signal is applied to the I/O pad 24, the PMOS transistor P2 is subjected to a 3.3 V gate voltage and a 5 V drain voltage. Since at the PMOS transistor P2 the gate voltage (3.3 V) is lower than the drain voltage (5 V), the PMOS transistor P2 will be switched into a conducting state, thereby causing the potential at Node 2 to be raised to 5 V, thus inhibiting the PMOS transistor P1) from being switched into a reverse conducting state. Moreover, the condition of the I/0 pad 24 receiving a 5 V input signal also causes the PMOS transistor P6 to be switched into a conducting state, thereby causing the output voltage at the floating N-well 22 also to be 5 V. This then causes the diode D1 to be turned into a non-conducting state. As a result of this, the diode D2 between the drain of the PMOS transistor P1 and the N-well is not subjected to a large current. Therefore, the improved I/O buffer of FIG. 1 represents a solution to the problem of the I/O buffer of FIG. 1.
There are, however, still some drawbacks in the foregoing I/O buffer of FIG. 2. When this I/O buffer operates in input mode and the input signal at the I/O pad 24 is switched from 5 V to 0 V, the voltage at the floating N-well 22 should be set at 3.3 V. In reality, however, the voltage at the floating N-well 22 is lower than 3.3 V due to the following reasons. First, the condition of the I/O pad 24 receiving a 0 V input signal causes the PMOS transistor P6 to be switched into a non-conducting state; second, the PMOS transistor P4 is switched into a non-conducting state when the I/O buffer is operating in the input mode; third, a parasitic capacitor C1 exists between the floating N-well 22 and the I/O pad 24; fourth, the diode D3 that exists between the source of the PMOS transistor P1 and the floating N-well 22 will be turned into a conducting state when the voltage at the floating N-well 22 drops to 3.3--V.sub.D (where V.sub.D is about 0.5-0.6 V), which causes the voltage at the floating, N-well 22 to latch at 3.3--V.sub.D and not be retained at 3.3 V. This situation causes a latchup to the IC device, which can easily cause burn-out of the IC device.
When the I/O buffer is operating in output mode, the I/O pad 24 can be switched to the 3.3 V output voltage state simply by issuing OEN=0 and Dout=1 to respectively put Node 1 and Node 2 at 0 V state to thereby cause the PMOS transistor P1 to be switched into a conducting state and the NMOS transistor N1 to be switched into a non-conducting state. At the same time, the drain of the NMOS transistor N4, which is connected to the I/O pad 24, is also put into the 3.3 V state. Since the gate voltage at the NMOS transistor N4 is also 3.3 V, the source voltage at the NMOS transistor N4 is only about 2.3 V rather than 3.3 V, thus causing the voltage at Node 3 to be also 2.3 V. The voltage at Node 4 is therefore also 2.3 V when the NMOS transistor N5 is switched into a conducting state.
Furthermore, the output can be switched from 3.3 V to 0 V by issuing Dout=0 to cause the voltages at Node 1 and Node 2 to be raised from 0 V to 3.3 V. The voltage at Node 1, which is connected to the gate of the NMOS transistor N1, can be switched from 0 V to 3.3 V without problem. However, the voltage at Node 2, which is connected to the gate of the PMOS transistor P1, has a problem in the switching of its voltage state. This is because that the voltage at Node 2 is supplied from both the NMOS transistor N2 and the PMOS transistor P3, of which the NMOS transistor N2 has a faster switching speed. Therefore, during the time when the voltage at Node 2 is rising from 0 V to 3.3 V, the chance of the voltage state will slow down or even pause when the voltage reaches 2.3 V. Since the gate voltage at the PMOS transistor P3, i.e., the voltage at Node 4, is originally 2.3 V, it will not be promptly switched into a non-conducting state until the NMOS transistor N1 has been switched into a conducting state to cause the voltage at Node 3 to drop. This then causes the voltage at Node 4 to drop, thereby switching the PMOS transistor P3 into a conducting state, causing the voltage at Node 2 to exceed 2.3 V. As a result of this, the PMOS transistor P1 is switched into a non-conducting state. From the foregoing description, it is clear that the lengthy time required in the switching process will degrade the output performance of the I/O buffer. Moreover, since there exists a short period during which both the PMOS transistor P1 and the NMOS transistor N1 are in a conducting state, an instant short-circuit current can occur, which would cause damage to the I/O buffer.